VexRiscv is a FPGA-friendly 32-bit RISC-V CPU implementation written in SpinalHDL that generates synthesizable hardware descriptions for embedded systems.
The project addresses the need for a customizable, open-source processor core suitable for FPGA deployment. Rather than providing a fixed design, VexRiscv uses a plugin architecture that allows developers to compose CPU configurations by selecting and combining functional modules. This approach enables trade-offs between area usage, clock frequency, and feature completeness. The tool generates Verilog or VHDL from a SpinalHDL specification, which can then be synthesized for FPGA targets. The project includes example System-on-Chip implementations like Briey and Murax, support for running Linux, and integration with standard debugging tools including GDB, OpenOCD, and Verilator simulation.
VexRiscv suits projects requiring a soft processor core where design flexibility and FPGA resource efficiency matter more than fixed performance characteristics. It works well for embedded systems, custom SoCs, and research applications where the ability to enable or disable features like instruction caches, floating-point units, memory management, and branch prediction directly impacts feasibility. The tool is appropriate for developers comfortable with hardware description languages and FPGA workflows. The plugin system allows adding custom instructions and control status registers without modifying core logic, making it suitable for domain-specific extensions.
Development activity shows consistent engagement with the codebase through regular updates to the plugin ecosystem and architecture documentation. The project maintains comprehensive regression testing infrastructure and provides multiple pathways for interactive debugging via simulation. Documentation covers CPU parametrization, instantiation patterns, and the plugin extension mechanism in detail, indicating sustained effort to support adoption and customization by new users.
