XiangShan is an open-source high-performance RISC-V processor project written in Scala using the Chisel hardware description language.
The project addresses the challenge of designing high-performance RISC-V processors by applying agile development methodology to chip design. It provides a complete processor implementation with multiple stable microarchitectures, each representing an iteration of the design. The tool encompasses the full stack needed for processor development, including design specification, functional verification, debugging, and performance validation capabilities.
XiangShan suits organizations and researchers working on RISC-V processor development who want access to a mature, open-source reference implementation. The project is appropriate for those studying high-performance processor design, building custom RISC-V systems, or contributing to open processor development. The repository includes comprehensive documentation covering design details and usage guidance, with ongoing translation efforts to support a broader audience.
The project maintains multiple active branches representing different microarchitecture generations, with Kunminghu representing the current third-generation design under active development. The codebase includes published research demonstrating the effectiveness of the agile methodology applied to processor design, with artifacts from that work made available for reproducibility. The project operates through public communication channels including a mailing list with archived discussions, indicating sustained community engagement and accessibility for external contributors.
