Repository Issue Activity (beta)

#6527 `fcvt.d.w` (int32→float64) spuriously raises the invalid (`NV`) fflag — kunminghu-v3

#6536 `vmadc.vi` zeroes mask-destination tail bits

#6407 Vector load doesn't trigger illegal instruction trap when VSEW is invalid

#6528 Single-precision FP op reads an improperly NaN-boxed source register as raw bits instead of the canonical NaN — kunminghu-v3

#6427 TopDownCounters object refactoring thoughts

#6526 LoadQueueRAWSize default (56) violates its own documented power-of-2 constraint

#6525 [Bug] NewLoadUnit S2 prefetchTrain.valid is not gated by kill

#6501 [Bug] `csrw minstret, X` followed by `csrr` reads X+1: the writing instruction's own retirement is added after the write

#6268 L1 DCache assertion: "failed too many SCs in a row, resv set addr always match"

#6068 WFI does not resume execution when some interrupts become pending

#6059 PTWFilterEntry: `inflight_counter` bit-width too small (use log2Up(Size+1) not log2Up(Size))

#5943 Incorrect `mtval` for faulting `vsse16.v` on kunminghu-v2

#6419 [Bug] dcsr.stopcount=1 does not stop minstret/mcycle in Debug Mode; only the instret/cycle read values are frozen

#6502 [Bug] With mnstatus.NMIE=0, a delegated S/U-mode exception becomes a critical error (hart stops) instead of trapping to stvec

#6497 mip.LCOFIP counter-overflow request is dropped when it coincides with a CSR write to mip/sip (mhpmevent.OF=1 but LCOFIP never set)

#6516 Scalar FP conversions (`fcvt.s.l`, `fcvt.lu.s`, …) do not raise the inexact (`NX`) fflag when the conversion rounds — kunminghu-v3

#6467 StoreQueue `deqPtr > rdataPtr` assertion fails at the physical-queue wrap boundary under vector stores

#6504 Single step: trigger at the branch target fires during the step (dcsr.cause=2 instead of 4)

#6500 WFI woken by an interrupt: if the next instruction is a load/store/CSR/fence it executes before the trap is taken (mepc = wfi+6/+8 instead of wfi+4)

#6505 haltreq / resethaltreq out of reset: no dedicated halt path, hart may commit instructions before entering Debug Mode

#6498 Misaligned load/store whose second half crosses into the non-canonical Sv39/Sv48 hole is not page-faulted; the high half aliases to the upper-half mapping

#6214 Pointer masking not applied to debug address-trigger comparison (MemTrigger compares raw vaddr)

#6420 CBO store triggers drop `mcontrol6.match` (block-index EQ only; `GE`/`LT` broken)

#6481 [Bug][Frontend] A return target misprediction no longer reaches BPU training after #6112

#5919 Reserved `vmv<nr>r.v` encodings are executed instead of being rejected