Yosys is a framework for RTL synthesis tools that converts hardware designs into optimized implementations.
The tool addresses the need to transform register-transfer level descriptions into synthesized hardware by providing a modular architecture where synthesis tasks are accomplished through combining existing algorithmic passes and synthesis scripts. Developers can extend functionality by adding custom passes to the C++ codebase. Yosys supports Verilog-2005 extensively and provides comprehensive SystemVerilog support through integration with external libraries, covering a synthesizable subset of IEEE 1800-2017 and IEEE 1800-2023 standards.
Yosys suits projects requiring flexible RTL synthesis where the ability to customize and extend the synthesis flow is valuable. It works well for teams building specialized synthesis tools, academic research, and open-source hardware projects. The tool is available through pre-built binary suites that bundle dependencies, or can be built from source. A commercial variant with enhanced SystemVerilog and VHDL parsing is available separately. Users interested in formal verification can pair Yosys with the SBY formal verification front-end.
The project maintains active documentation automatically built and published on Read the Docs. Community discussion occurs through a dedicated Discourse group. The tool is distributed under the ISC license, a GPL-compatible permissive license, with third-party components in included subdirectories under compatible terms.
