Repository Issue Activity (beta)

#3829 [BUG] PMP: empty TOR entry incorrectly causes access faults

#3828 five requested L1 DTLB ways silently provide four mappings

#3827 mie is read back unmasked from an un-reset register, so its non-writable bits are not read-only zero

#3826 mstatus.TW is gated on usingSupervisor instead of usingUser: an M+U hart cannot trap WFI from U-mode

#2348 mtval not written after ebreak

#3819 BOOM does not initialize io.core.rocc.mem.store_pending

#3815 [Bug] hedeleg writes are masked to zero in H-enabled Rocket

#3817 [Security] Hypervisor NonBlockingDCache does not invalidate DTLB for HFENCE.VVMA/GVMA

#3816 [Bug] First VS-mode `sstatus` read returns host FS/SD view instead of VS-visible state

#3814 [Bug] PMP cfg reset/readback exposes reserved R/W encoding after reset

#3812 [Bug] CSR: MPRV-mediated PMP fault raises wrong exception code (mcause=2 or 3 instead of 5 or 7)

#3811 [Bug] CSR: S-mode access to M-mode CSRs raises wrong exception code (mcause=1 instead of mcause=2)

#2944 Speedup remote bitbang server by setting TCP_NODELAY

#3810 [BUG] Rocket DefaultSmallConfig traps S-mode fetch from an X-only PMP region

#3809 [BUG] Rocket DefaultSmallConfig does not trap MPRV=S store denied by PMP

#3808 Rocket hangs instead of taking load page fault when PMP also denies the translated address

#3787 ASIdBits parameter always set to 0

#3784 ALU shiftReverse includes FN_ROR unconditionally, leaving residual logic when useZbb=false

#2760 APB Initiator with AHB Target through TLXbar. Edges seem to only support PutPartial(APB) PutFull(AHB)

#3750 How to enable many RoCC accelerators with RocketChip?

#3780 Interrupt Claim Process of PLIC and Rocket

#3770 make run-binary-debug failed, unable to generate complete waveform

#3779 make verilog fails

#3778 [Bug Report] Illegal CSR access to mtval2 does not raise exception in Rocket

#3777 [Bug Report] Architectural state updates for REM/REMUW instructions are misattributed to incorrect PCs in trace logs