Repository Issue Activity (beta)

#5243 SRAM.masked broken when the mask is a constant of all 1s

#4402 Update docs/README.md

#5450 `"` in propassert is not properly escaped

#5411 [firrtl] Hardware with nested direction generates failing firrtl with Reg / RegNext

#5430 Naming Plugin and Object Pattern

#5418 MultiClockSpec chiselTest fails with recent Verilator version

#5415 Update to Chisel Technical Charter

#5100 Chisel 8 Tracker

#5407 Better error message for misuse of Domain association to ports

#3317 Broken Links on Chisel-Lang.org docs

#5406 "Plain"-style verilog assertions/assumes/covers for FV

#4246 ChiselSim waveforms

#5383 ModuleChoice does not connect implicit clock/reset to FixedIOModule targets

#4444 PriorityMux drops arguments if input sequences are not the same size

#5357 "-disable-all-randomization" can't work when the module with RequireAsyncReset

#5335 [ChiselSim] Flag `--trace-threads` is deprecated since Verilator v5.048

#4433 SyncReadMem ruw (ReadUnderWrite) parameter has no effect

#4775 Error When Connecting Analog-Only Bundle to Verilog Blackbox

#5249 could we support scala3 ，upgrade the core code just could use Claude？

#5244 [doc] Add documentation about layer-under-layer errors and how to mitigate

#5233 Invalid FIR emission with Instance choice

#1901 Chisel compiled to system verilog

#3677 Chisel5.1.0 cannot emit verilog

#5231 suffix always be "sv"

#5230 ChiselSim cannot deal with 0-width signals and `DontCare` values