brunolevy/learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

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Summary Information

Updated 8 minutes ago
Added to GitGenius on September 18th, 2026
Created on May 27th, 2020
Open Issues & Pull Requests: 59 (+0)
GitHub issues: Enabled
Number of forks: 352
Total Stargazers: 3,690 (+0)
Total Subscribers: 92 (+0)

Repository Insights (GitGenius)

Median issue/PR response: 38.8 days
Mean response time: 71.2 days
90th percentile: 276.4 days
Tracked items: 5

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Issue Activity (beta)

Open issues: 11
New in 7 days: 1
Closed in 7 days: 0
Avg open age: 422 days
Stale 30+ days: 9
Stale 90+ days: 7

Recent activity

Opened in 7 days: 0
Closed in 7 days: 0
Comments in 7 days: 0
Events in 7 days: 0

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Detailed Description

learn-fpga is a teaching resource for learning FPGA design, processor architecture, and RISC-V implementation using affordable hardware.

The project addresses the challenge of making FPGA and processor design education accessible by providing a complete learning path grounded in practical, low-cost hardware. It centers on FemtoRV, a minimalistic RISC-V CPU implementation written in readable Verilog that directly follows the RISC-V specification. The elementary version spans only 400 lines of documented code, making the design transparent and understandable. The repository includes progressively more complex variants and a companion system-on-chip with drivers for common peripherals like UART, LED matrices, OLED displays, SPI RAM, and SD cards. The teaching approach moves from the simplest designs, such as LED blinkers, through to fully functional RISC-V cores capable of computation and graphics rendering. The project also demonstrates integration with LiteX, a framework for assembling SoCs by composing components in Python, showing how FemtoRV can be used as a processor within larger systems.

This resource suits educators and students who want hands-on experience with processor design and FPGA tooling without substantial budget constraints. The minimal hardware requirements mean a complete learning setup costs around forty dollars per student. The step-by-step tutorial structure, progressing from basic digital logic to pipelined processor design, makes it suitable for courses ranging from introductory digital design to advanced computer architecture. The inclusion of LiteX examples provides a bridge to more sophisticated SoC design practices for those ready to move beyond the educational core.

Development activity shows consistent engagement with the teaching mission. The repository maintains a structured tutorial progression with multiple episodes covering distinct architectural concepts. The codebase includes both minimal and elaborate processor variants, indicating iterative refinement of the educational material. The direct integration with LiteX and active support within that ecosystem demonstrates ongoing relevance to contemporary FPGA design practices.